Design and Frequency Response of Digital Phase Locked Loop (dpll) Using Simulink

Design and simulation of Digital PLL has been illustrated in this paper. The Digital PLL is given signal of 400 MHz to 900 MHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the Digital PLL blocks are designed and simulated using Simulink. It is verified that Digital PLL is stable with a phase margin of 91.1 degree which satisfy the transfer function correctness. KeywordsDPLL, Phase frequency detector (PFD), Voltage controlled oscillator (VCO), Loop filter, Simulink. Introduction The phaselocked loop (PLL) constitutes an important “Mixed-Signal” device used in transceivers, communication systems etc. The PLL recovers clock from digital data signals, recovers the carrier from satellite transmission signals, performs frequency and phase modulation and demodulation and synthesize exact frequencies for receiver tuning. The bestknown application of PLLs is clock recovery in communication, frequency synthesis, tracking filter, and phase modulation. Other applications include disk drive control, harmonic compensation, and motor control. The digital PLL (DPLL) is a type of PLLs used to synchronize digital signals. While DPLLs input and outputs are typically digital (square wave), they do have internal functions, which are dependent on analog signals. Thus they are basically known as classical DPLLs. The digital phase locked loop (DPLL) is a closed loop control system that has the ability to generate a feedback signal whose phase and frequency are aligned to the phase and frequency of the reference signal at locked condition [1]-[3]. The charge pump phase locked loop (CPPLL) is widely used for its frequency sensitive error signal, as it can aid acquisition when the loop is out of lock [1].It consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF) and a voltage controlled oscillator (VCO) in the forward path and a frequency divider (FD) in the reverse path. When the DPLL is in lock, there is a small phase difference between the two input signals of the phase frequency detector [2]. According to that error signal, the CP either increases or decreases the amount of charge to the LF. This amount of charge either speeds up or slows down the VCO and shifts the VCO from its free running frequency and keeps the loop in lock [3]. . PFD (Phase-Frequency Detector) The Simulink model of the conventional sequential tri-states D flip-flop based PFD is shown in the Figure 1. A PFD with three states is widely used because of its wide linear range and ability to capture phase and frequency [1]. The reference signal and the feedback signal are given to the two input clock of the D flipflop.